1. Technical Field
The present invention relates to a structure, and method of formation, including a patterned layer over a dielectric layer, and a second dielectric layer preferentially including a thermoplastic fluoropolymer (TFP) over the patterned layer, wherein the patterned layer typically includes a chrome pattern on a copper pattern with dielectric material plugging otherwise void space within the patterned layer, and wherein the chrome pattern prevents processing-induced delamination of the second dielectric layer from the patterned layer.
2. Related Art
A laminate (e.g., a chip carrier) made of a dielectric material typically includes internal metalized layers, such as a ground plane, a signal plane, and a power plane. The ground plane, which may include inter alia a copper-invar-copper sandwich of planes, serves to provide a common voltage level of zero volts. Additionally, the ground plane is a large, mechanically stable structure to which small structures within the substrate may be registered for dimensional control during the laminate fabrication process. The signal plane, which may be disposed inter alia between the ground plane and the power plane, is an internal circuitized layer of metallic fine structure such that the metallic fine structure comprises a small percentage (e.g., 5%) of the volume of the signal plane.
The power plane supplies one or more fixed voltages to a circuit, or to an electronic component, that is electrically coupled to the power plane. A power plane includes a metal sheet, such as a copper sheet, which comprises a large percentage of the volume of the power plane (e.g., 95%). A surface of the power plane facing toward the ground plane is an xe2x80x9cinner surface,xe2x80x9d and a surface of the power plane facing away from the ground plane is an xe2x80x9couter surface.xe2x80x9d A power plane may include a clearance hole plugged with the dielectric material (xe2x80x9cdielectric plugxe2x80x9d). A plated though hole (PTH) may pass through the power plane of the laminate such that the PTH is encapsulated within the dielectric plug of the clearance hole, resulting in electrical insulation of the PTH from the metal sheet of the power plane.
If the dielectric material of the laminate includes a thermoplastic fluoropolymer (TFP), such as a teflon (e.g., a Rogers 2800 material from the Rogers Corporation), there is a propensity for delamination between the outer surface of the power plane and the dielectric material during process steps in the fabrication of the laminate. Inasmuch as the metal sheet of the power plane may comprise a large percentage (e.g., 95%) of the volume of the power plane, the delamination may have a significant adverse impact on the structural integrity of the laminate. In contrast, there are generally no material delamination concerns relating to the signal plane, since the metallic fine structure of the signal plane comprises only a small percentage (e.g., 5%) of the volume of the signal plane. A source of the delamination relates to the heat generated by laser formation of through holes in the laminate. The TFP material has a low melting point (e.g., the Rogers 2800 material melts at about 327xc2x0 C.) and readily melts within a localized space near the laser-generated through holes. The local melting of the TFP material and the swelling effect of the high local temperature may cause local delamination of the TFP material from the power plane surfaces. The delamination effect from the laser drilling is mitigated by the use of an oxide pre-treatment of the copper surfaces of the power plane and is sufficiently effective to prevent delamination of the dielectric from the inner surface of the power plane. Nonetheless, the outer surface of the power plane is subject to another source of delamination, namely chemical attack from moisture and chemicals used in various plating, etching, and surface preparation processing steps. Such chemical attack is particularly relevant for TFP dielectrics having a filler material, such as silica or quartz, which are used for structural reinforcement. Inasmuch as a discontinuity exists between the TFP material and the silica particles, there are numerous percolation paths within the dielectric material through which moisture and processing chemicals may flow. The percolation paths enable processing chemicals to easily access the interface between the dielectric layer and the outer surface of the power plane, resulting in degradation of adhesion between the dielectric material and the outer surface of the power plane. The delamination resulting from chemical attack is not a local effect and potentially impacts the entire interface between the outer surface of the power plane and the dielectric layer formed on the outer surface. The problem of chemical attack does not materially affect the inner surface of the power plane, because the power plane itself acts as a percolation barrier to chemical percolation. Additionally, the ground plane serves as a registration reference for dimensional stability purposes, as discussed supra. Accordingly, the fabrication process starts with providing the ground plane and serially adding structural features outward from the ground plane until the laminate is fully developed. Thus, after the ground plane is laminated to the dielectric, chemicals from subsequent processing of the laminate have access primarily to the outer surface, rather than the inner surface, of the power plane.
A method is needed to prevent delamination at the interface between the outer surface of the power plane and the dielectric layer formed on the outer surface.
The present invention provides a method for forming an electrical structure, comprising:
providing a layered structure, including a dielectric layer, a metal layer on the dielectric layer, and a metallic layer on the metal layer;
forming a patterned layer on the dielectric layer, including etching through the metallic layer, and etching an exposed portion of the metal layer; and
plugging a void space within the patterned layer with a dielectric that includes a thermoplastic fluoropolymer (TFP) material, wherein a plugged pattern is formed; and
forming a second dielectric layer on the patterned layer, adhesively bonded to a top surface of the patterned layer, wherein the second dielectric layer includes the TFP material.
The present invention also provides a method for forming an electrical structure, comprising:
providing a layered structure, including a dielectric layer, a metal layer on the dielectric layer, and a chrome layer on the metal layer; and
forming a patterned layer on the dielectric layer, including etching through the chrome layer, and etching an exposed portion of the metal layer.
The present invention provides an electrical structure, comprising:
a dielectric layer;
a patterned layer on the dielectric layer, including a metal pattern on the dielectric layer, a metallic pattern on the metal pattern, and a plugged pattern having a dielectric material within a remaining space of the patterned layer; and
a second dielectric layer on the patterned layer, adhesively bonded to a top surface of the patterned layer, wherein the second dielectric layer includes the dielectric material.
The present invention has the advantage of preventing delamination at an interface between the outer surface of a patterned metallic layer and a dielectric layer adhesively formed on the patterned metallic layer, wherein the dielectric layer includes a TFP material.
Noting that a method of the present invention includes etching through a metallic layer that preferentially comprises chrome, the present invention discloses an effective method for etching chrome located under a hole in a photoresist layer. The disclosed method advantageously etches the chrome without attacking the photoresist. The disclosed method, as applied to very small holes in the photoresist layer, advantageously overcomes surface tension that would otherwise prevent the etchant from fully contacting the chrome material to be etched. The disclosed method advantageously increases the wettability of the sidewall of the hole in the photoresist layer, which facilitates improved coverage of the chrome surface area by the etchant. The disclosed method advantageously overcomes adverse electrochemical effects caused by etching a part while the part is contained within a metallic frame.